基于verilog的简单逻辑电路

 半加器：

使用门：

module ADD_half(output c_out, sum,  input a,b );

    xor (sum,a,b);

    and (c_out,a,b);

endmodule

使用抽象语句：

module ADD_half_nogate(output cout,sum, input a,b,cin);

assign      sum=a^b;

assign     cout=a&&b;

endmodule

使用门定义去编写逻辑电路过于麻烦，以下都电路只会使用逻辑符号来描述。

全加器：

module ADD_full(output c_out,sum, input a,b,cin);

wire w1, w2, w3;

ADD_half_nogate M1(w2,w1,a,b);

ADD_half_nogate M2(w3,sum,cin,w1);

assign c_out=w3||w2;

   

endmodule

testbench:

module t_Add();

wire sum, c_out;

reg a, b,cin;

ADD_full M1(c_out,sum,a,b,cin);

 initial begin

   $dumpfile("dump.vcd");

   $dumpvars;

 end

initial begin

    #100 $finish;

end

initial begin

    #10 a=0 ;b=0;cin=1;

    #10 b=1;

    #10 a=1;

    #10 b=0;

end

endmodule

2位选择器：

module multiplexer(output mux_out , input sel, a,b);

assign mux_out=(sel)?a:b;

endmodule

testbench：

module t_mux();

wire mux_out;

reg a, b,sel;

  multiplexer M1(mux_out,sel,a,b);

 initial begin

   $dumpfile("dump.vcd");

   $dumpvars;

 end

initial begin

    #100 $finish;

end

initial begin

    #10 a=0 ;b=1;sel=1;

    #10 sel=0;

 

end

endmodule

SR 锁存器：

module latch_sr (en,s,r,q,q_bar);

output q,q_bar;

input s,en,r;

assign q_bar=!q ;

assign q=~en?0:r?0:s?1:q ;

endmodule

testbench:

module sr_tb();

wire q,q_bar;

reg s,en,r;

latch_sr sr(en,s,r,q,q_bar);

 initial begin

   $dumpfile("dump.vcd");

   $dumpvars;

 end

initial begin

    #200 $finish;

end

initial begin

    #10 en=0 ;s=0;r=0;

    #10 en=0 ;s=0;r=1;

    #10 en=0 ;s=1;r=0;

    #10 en=0 ;s=1;r=1;

    #10 en=1 ;s=0;r=0;

    #10 en=1 ;s=0;r=1;

    #10 en=1 ;s=1;r=0;  

    #10 en=0 ;s=1;r=0;

end

endmodule

Dff触发器：

module dff(q,q_bar,data,clk);

output reg q;

output q_bar;

input data ,clk;

assign q_bar=!q;

always @ (posedge clk)

 begin

    q<=data;

 end

endmodule

testench：

module tb_DFF();

reg data,clk;

wire q,q_bar;

dff dff(q,q_bar,data,clk);

initial begin

  clk=0;

     forever #10 clk = ~clk;  

end

 initial begin

   $dumpfile("dump.vcd");

   $dumpvars;

 end

initial begin

    #1000 $finish;

end

initial begin

    #100 data=0;

    #100 data=1;

    #100 data=1;

    #100 data=0;

    #100 data=0;

    #100 data=0;

    #100 data=1;

    #100 data=1;

end

endmodule

移位寄存器：

module four_bit_shifter(A,E,clk,rst);

output  reg A;

reg B,C,D;

input clk,rst,E;

always @ (posedge clk or posedge rst) begin

  if(rst)begin

    A<=0;

    B<=0;

    C<=0;

    D<=0;

  end

  else begin

    A<=B;

    B<=C;

    C<=D;

    D<=E;

  end

end

endmodule

testbench:

module t_shifter();

wire A;

reg E,clk,rst;

four_bit_shifter M1(A,E,clk,rst);

 initial begin

   $dumpfile("dump.vcd");

   $dumpvars;

 end

initial begin

  clk=0;

     forever #10 clk = ~clk;  

end

initial begin

    #200 $finish;

end

initial begin

    #10 E=0;rst=0;

    #10 E=1;

    #10 E=1;

    #10 E=0;rst=0;

    #10 E=0;rst=0;

    #10 E=1;

    #10 E=1;

    #10 E=1;

    #10 E=0;

    #10 E=0;

    #10 E=0;

    #10 E=0;

    #10 E=1;

    #10 E=1;

    #10 E=0;

    #10 E=1;

    #10 E=0;rst=1;

    #10 E=0;rst=0;

end

endmodule