Synthesis based on Cadence Tools
Cadence所用的Synthesis工具为Genus。
目前的使用感受，相对于Design Compiler而言，有以下几个明显的优缺点。
优点：1.不用db文件，lib文件可以直接使用。
2.可以添加tech lef、*.lef和qrc file或者Capacitance table来更加贴近真实情况, 和Place and Route连接紧密，如若可提供上述的文件，便可直接利用 commad：
syn_opt -physical
进行Placement。
缺点：1.SDC文件有些指令并不能完全读取，需要更改，而Gensu本身所提供的Timing constraints 指令又太少。
2.Design Compiler有时即便读取的Verilog有错误也可继续执行任务。Genus会直接终止任务。
3.运行速度上没有Design Compiler快。
以下为我所使用的脚本：（待更新）
include setting.tcl
# set_attribute information_level 6 ;# See a lot of warnings.
set_attribute max_cpus_per_server 16 /
set basename exu
set runname RTL ;# name appended to output files
include spc.tcl
#
foreach file_name $file_names {
read_hdl $file_name
}
elaborate ${basename}
#read timing constraint
set_attribute max_fanout 6 $basename
read_sdc constraint.sdc
if {[llength [all::all_seqs]] > 0} {
define_cost_group -name I2C -design $basename
define_cost_group -name C2O -design $basename
define_cost_group -name C2C -design $basename
path_group -from [all::all_seqs] -to [all::all_seqs] -group C2C -name C2C
path_group -from [all::all_seqs] -to [all_outputs] -group C2O -name C2O
path_group -from [all_inputs] -to [all::all_seqs] -group I2C -name I2C
}
define_cost_group -name I2O -design $basename
path_group -from [all_inputs] -to [all_outputs] -group I2O -name I2O
# check that the design is OK so far
check_design -unresolved
#report timing -lint
# Synthesize the design to the target library
synthesize -to_generic -eff high
synthesize -to_mapped -effort high
set_attribute syn_opt_effort high
syn_opt -physical
write_snapshot -outdir $innovus_log_path -tag syn_opt
report_summary -outdir $innovus_log_path
include where_to_result.tcl
report_timing -from [all_registers] -to [all_registers]
exit
setting.tcl:
set innovus_log_path "output_innovus_file_path"
# set log_path "/home/shi/cadence/GENUS/log/ocl15/"
set log_path "your report saving path"
set Timing_log_path "your timing report saving path"
#set model_name "your_Model_name"
set_attribute hdl_search_path {/home/shi/OpenSPARCT2.1.3/} ;# Search path for Verilog files
set_attribute time_recovery_arcs true /
set_attribute timing_use_ecsm_pin_capacitance true /
# ::legacy::set_attribute write_vlog_empty_module_for_logic_abstract false /
set_attribute lp_insert_clock_gating true /
set_attribute lp_insert_discrete_clock_gating_logic true /
set_attribute leakage_power_effort high /
# Target Library
set_attribute lib_search_path {your search path}
set_attribute library [ your lib ];
set_attribute lef_library [tech.lef *.lef ]
set_attribute qrc_tech_file [you qrc_file]
where_to_result.tcl:
report timing > $log_path${basename}_${runname}_${model_name}_timing_test_1G_new_1.rep
report gates > $log_path${basename}_${runname}_${model_name}_cell.test_1G_new_1.rep
report power > $log_path${basename}_${runname}_${model_name}_power.test_1G_new_1.rep
constrait.sdc:
#set clock frequency
set myClk your_clk_name
#Mhz or ghz , depend on model, use timing report to check it's G or M.
set clk_f 1.0
set myPeriod_ps [expr 1000/$clk_f] ;# Clock period
#timing constraint parameter
set myInDelay_ps value
set myOutDelay_ps value
set high_time [expr $myPeriod_ps / 2.0]
set default_setup_skew value
set default_hold_skew value
set default_clk_transition value
set default_clk_freq 1.0
set default_clk your_clk_name
set_max_fanout value
set_max_transition value
set critical_range value
set clock_transition value
set clk_port_pin $myClk
set clk_name $myClk
set clk_freq $clk_f
set setup_skew valueset hold_skew value
# set clock [define_clock -period ${myPeriod_ps} -rise 50 -fall 50 -name ${myClk} [clock_ports]]
# create_clock $clk_port_pin -period $myPeriod_ps -waveform [list 0 $high_time] -name $clk_name
create_clock -period $myPeriod_ps -waveform [list 0 $high_time] [get_ports $clk_name]
set_clock_uncertainty -setup $setup_skew [get_clocks $clk_name]
set_clock_uncertainty -hold $hold_skew [get_clocks $clk_name]
set_clock_transition $clock_transition [get_clocks $clk_name]
set_dont_touch_network $clk_name
# external_delay -input $myInDelay_ps -clock ${myClk} [find / -port ports_in/*]
# external_delay -output $myOutDelay_ps -clock ${myClk} [find / -port ports_out/*]
set_input_delay $myInDelay_ps -clock $clk_name [all_inputs]
set_output_delay $myOutDelay_ps -clock $clk_name [all_outputs]
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