Design Compiler and TCL language based on Linux Terminal

Terminal command: dc_shell -f compile.tcl 

TCL  file Example:

set design_name example

set log_path "/home/usr/design/log/"

set link_library "* /home/usr/Tmp/example.db"

set target_library "/home/usr/Tmp/example.db"

set wire_library_file  {/home/usr/Tmp/example.db}

set wire_library example

lappend search_path "../../Src/"

# Working directory

define_design_lib WORK -path "./work"

analyze -format sverilog  example.sv

elaborate example  -work WORK

current_design $design_name

#clock=1/period(ps)

create_clock -period 2000 clk

set_max_area 0

#timing setting

set max_transition   7.275162324

set default_input_delay  7.275162324

set default_output_delay 9.700216431

set critical_range      14.55032465

set wire_model_name      05x05

set wireload_mode      top

set symbol_library {}

set dont_use_cells 0

compile -ungroup_all

redirect [format $log_path/power.rep] { report_power }

# write -f ddc -o read.ddc -hier $design_name

link

exit